| Instruction Cache Leakage Reduction by Changing Register Operands and Using Asymmetric SRAM Cells | |
Abstract/OtherAbstract
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Great Lakes Symposium on VLSI (GLSVLSI) 2008 : May 4-6, 2008 : Orlando, Florida, Share of leakage in cache memories is increasing with technology scaling. Studies show that most stored bits in instruction caches are zero, and hence, asymmetric SRAM cells which dissipate less leakage when storing 0, effectively reduce leakage with negligible performance penalty. We show that by carefully choosing register operands of instructions, it is possible to further increase the number of 0 bits, and hence, increase leakage savings in instruction cache. This compiler technique is performed off-line and introduces absolutely no delay penalty since processor registers are all the same. Experimental results of our benchmarks show up to 33% (averaging 30.35%) improvement in leakage. |
Authors
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Goudarzi, Maziar, Ishihara, Tohru, 石原, 亨, イシハラ, トオル |
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Contributors
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System LSI Research Center, Kyushu University, 九州大学システムLSI研究センター |
Publication Detail
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Publisher : - Type : 会議発表論文, Conference Paper Format : 249828 bytes, application/pdf |
Date Detail
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2008-05-26, 2008-05-26, 2008-05-06 |
Subject
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Semiconductor Memory, Static memory, SRAM, Cache memory, Compilers, Optimization, Algorithms, Measurement, Design, Experimentation |
Coverage
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- |
Relation
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http://www.c.csce.kyushu-u.ac.jp/SOC/index_j.html, http://www.glsvlsi.org/ |
Source
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- |
Copyright Information
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Other Details
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Languages : en |
Export Citation
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