| Analog CMOS implementation of a multilayer perceptron with nonlinear synapses. | |
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MedLine Citation:
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PMID: 18276449 Owner: NLM Status: In-Data-Review |
Abstract/OtherAbstract:
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A neurocomputer based on a high-density analog integrated circuit developed in a 3 mum CMOS technology has been built. The 1.6 mmx2.4 mm chip contains 18 neurons and 161 synapses in three layers, and provides 16 inputs and 4 outputs. The weights are stored on storage capacitors of the synapses. A formalization of the error back-propagation algorithm which allows the use of very small nonlinear synapses is shown. The influence of offset voltages in the synapses on the circuit performance is analyzed. Some experimental results are reported and discussed. |
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Authors:
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J B Lont; W Guggenbuhl |
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Publication Detail:
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Type: Journal Article |
Journal Detail:
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Title: IEEE transactions on neural networks / a publication of the IEEE Neural Networks Council Volume: 3 ISSN: 1045-9227 ISO Abbreviation: IEEE Trans Neural Netw Publication Date: 1992 |
Date Detail:
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Created Date: 2008-02-15 Completed Date: - Revised Date: - |
Medline Journal Info:
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Nlm Unique ID: 101211035 Medline TA: IEEE Trans Neural Netw Country: United States |
Other Details:
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Languages: eng Pagination: 457-65 Citation Subset: - |
Affiliation:
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Electron. Lab., Swiss Federal Inst. of Technol., Zurich. |
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From MEDLINE®/PubMed®, a database of the U.S. National Library of Medicine
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